ARM EN0-001 Online Practice Questions and Exam Preparation

ARM EN0-001 Online Questions & Answers

• Question 121:

  Which of the following best describes the relationship between Tightly Coupled Memories (TCM), Level 1 (L1) and Level 2 (L2) cache memory systems?

  A. TCMs are a part of only L1 cache system
  B. TCMs are a part of only L2 cache system
  C. TCMs are part of both L1 and L2 cache systems
  D. TCMs are not part of either L1 or L2 cache systems
  D. TCMs are not part of either L1 or L2 cache systems

• Question 122:

  When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?

  A. Writes dirty data cache lines to memory
  B. Reloads dirty data cache lines from memory
  C. Speculatively preloads data into the cache
  D. Writes dirty data cache lines to memory and marks those lines as invalid
  A. Writes dirty data cache lines to memory

• Question 123:

  What is an "Entry point" in an application?

  A. A place where execution can start
  B. The location of the main () function
  C. The lowest address contained in a program image
  D. A location where the linker can store additional information
  A. A place where execution can start

• Question 124:

  How many ARM core registers and PSRs (Program Status Registers) are available to the programmer in User mode on a Cortex-A9?

  A. 16
  B. 17
  C. 18
  D. 32
  B. 17

• Question 125:

  What will be the contents of R2 after the execution of the following piece of code? LDRR1, =0xAABBCCDD MOV R2, #0x4 ANDSR1, R1, #0x4 ADDNE R2, R2, #0x4

  A. R2 = 0x4
  B. R2 = 0x8
  C. R2 = 0xAABBCCDD
  D. R2 = 0xAABBCCD4
  B. R2 = 0x8

• Question 126:

  In Thumb state an ARMv7-A processor can execute:

  A. Only 16-bit Thumb instructions.
  B. Only 32-bit Thumb instructions.
  C. 16-bit and 32-bit Thumb instructions.
  D. 32-bit Thumb and certain ARM instructions.
  C. 16-bit and 32-bit Thumb instructions.

• Question 127:

  Which of the following is an optional extension to the ARMv7-A architecture?

  A. VFP
  B. The System Control Coprocessor (CP15)
  C. Support for memory barriers
  D. A Memory Protection Unit conforming to the PMSA
  A. VFP

• Question 128:

  In which of the following situations would you use a mutex to avoid synchronization problems?

  A. A single-threaded application needs to manage two separate UART peripherals
  B. Two independent threads running on a single processor both need to access a single UART
  C. In a dual-core system, a UART is accessed by a single thread running on one of the processors
  D. In a dual-core system, processor A needs to access UART A and processor B needs to access UART B
  B. Two independent threads running on a single processor both need to access a single UART

• Question 129:

  In the CPSR, 1=0 and F=1. Which of the following is TRUE in this case?

  A. Both IRQs and FIQs are enabled
  B. Both IRQs and FIQs are disabled
  C. IRQs are disabled and FIQs are enabled
  D. IRQs are enabled and FIQs are disabled
  D. IRQs are enabled and FIQs are disabled

• Question 130:

  When using an Operating System, which instruction is used by user code to request a service from the kernel?

  A. BLX
  B. RFEFD
  C. SRSFD
  D. SVC
  D. SVC