EN0-001 Real Exam Questions and Verified Answers

Question 1 Single choice

In the Generic Interrupt Controller (GIC), when an interrupt is requested, but is not yet being handled, it is in which of the following states?

A
Inactive
B
Active
C
Pending
D
Edge-triggered

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Correct answer: C

Question 2 Single choice

What is the value of R2 after execution of the following instruction sequence?

MOV R3, #0xBA

MOV R2/#0x10

BIC R2, R3, R2

A
R2 = 0xBB
B
R2 = 0xCB
C
R2 = 0xAA
D
R2 = 0xCC

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Correct answer: C

Question 3 Single choice

Which one of the following statements best describes the function of vector catch logic?

A
It traps writes to the memory containing the vector table
B
It provides additional resources for debugging exception handlers
C
It provides configurable exception priorities on an ARM processor
D
It provides an improved mechanism for an application to handle exceptions

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Correct answer: B

Question 4 Single choice

According to the AAPCS (with soft floating point linkage), when the caller "func" calls sprintf, where is the value of the parameter "x" placed?

#include <stdio.h>

void func(double x, int i , char *buffer)

sprintf(buffer, "pass %d: value = %f\n", i, x); }

A
Split between register R3 and 4 bytes on the stack
B
Split between registers R3 and R4
C
8 bytes on the stack
D
VFP Register D0

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Correct answer: C

Question 5 Single choice

In a symmetric multi-processing (SMP) software architecture, which of the following pairs of statements are TRUE? (Select the option in which BOTH statements are TRUE).

A
The roles of individual cores are determined dynamically. Each core has its own set of external peripherals.
B
Each core has the same view of memory and shared peripherals. Any user application, process or task can be scheduled to run on any core.
C
The roles of individual cores are statically determined by the system designer. Hardware must be implemented to provide cache coherency between the cores.
D
Each core has the same view of memory and peripherals. The roles of individual cores are statically determined by the system designer.

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Correct answer: B

Question 6 Single choice

What architecture does the ARM11 MPCore implement?

A
ARMv6
B
ARMv6K
C
ARMv7-A
D
ARMv7-A with the Multiprocessing Extensions

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Correct answer: B

Question 7 Single choice

What are the values of the NZCV bits in the CPSR after executing the following instructions?

LDR R0, = 0xFFFFFFFF

ADDS R0, R0, #1

A
0101
B
0110
C
1001
D
1010

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Correct answer: B

Question 8 Single choice

An undefined instruction will cause an Undefined Instruction exception to be taken when:

A
It is fetched.
B
It is decoded.
C
It is executed.
D
It writes back its results.

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Correct answer: C

Question 9 Single choice

A simple method of measuring the performance of an application is to record the execution time using the clock on the wall or a wristwatch.

When is this method INAPPROPRIATE?

A
When executing the software using a simulation model
B
When the processor is a Cortex-R4
C
When instruction tracing is enabled
D
When the processor is not executing instructions from cache

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Correct answer: A

Question 10 Single choice

When linking with the standard C library, which library functions MUST be redefined in order to port your code to a new piece of production hardware?

A
Functions that are not compliant with the ISO C library standard
B
Functions that are not compliant with the 1985 IEEE 754 standard for binary floating-point arithmetic
C
Target-dependent functions which use semihosting
D
Functions called implicitly by the compiler

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Correct answer: C