ARM EN0-001 Online Practice Questions and Exam Preparation

ARM EN0-001 Online Questions & Answers

• Question 141:

  In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)

  A. VA == PA; No address translations; instructions and data are not cached
  B. VA! = PA; No address translations; instructions may be cached but not data
  C. VA == PA; Address translations take place; data may be cached but not instructions
  D. VA == PA; No address translations; instructions may be cached but not data
  D. VA == PA; No address translations; instructions may be cached but not data

• Question 142:

  When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)

  A. Coherency management between all L1 data caches
  B. Broadcast of some inner-shared cache and TLB maintenance operations
  C. Broadcast of some outer-shared cache and TLB maintenance operations
  D. Coherency management between all L1 instruction caches
  E. Coherency management between all external caches
  A. Coherency management between all L1 data caches
  B. Broadcast of some inner-shared cache and TLB maintenance operations

• Question 143:

  Which of the following memory attributes, specified in a translation table entry, could be used to protect a page containing a read-sensitive peripheral from speculative instruction fetches?

  A. S (Secure)
  B. nG (non-Global)
  C. xN (Execute Never)
  D. AP (Access Permission)
  C. xN (Execute Never)

• Question 144:

  As part of the ABI specification, the AAPCS defines which of the following?

  A. How many levels of nested function calls are permitted on ARM systems
  B. How to measure the maximum amount of stack required by an application
  C. On which mode's stack you need to save the return address in a non-leaf function
  D. Which registers need to be preserved by a function
  D. Which registers need to be preserved by a function

• Question 145:

  For Cortex-A series cores, what instruction(s) are recommended to implement a mutex or semaphore?

  A. SWP and SWPB
  B. DSB and ISB
  C. LDREX and STREX
  D. DMB
  C. LDREX and STREX

• Question 146:

  In which of these cases would code have better performance when compiled for Thumb state than when compiled for ARM state?

  A. When the processor has no data cache
  B. When the code involves many shifting operations
  C. When the code has many conditionally executed instructions
  D. When the processor can only fetch instructions 16-bits at a time
  D. When the processor can only fetch instructions 16-bits at a time

• Question 147:

  The following pair of functions implement a simple mutex spinlock which might be used to protect a critical code section in a multi-threaded application. The address of the lock variable is in r0.

  

  In order to minimize power while waiting for the lock to be available. SEV and WFE instructions can be used to place the processor in a low power state while waiting for the lock to become available. At which points should these instructions be placed?

  A. WFENE at , SEV at
  B. WFEEQ at SEV at
  C. WFE at SEV at WFENE at
  D. SEV at
  B. WFEEQ at SEV at

• Question 148:

  If a 16-bit Thumb instruction causes a Data Abort, which instruction would return from the handler to the instruction after the one that caused the data abort?

  A. SUBS PC. LR
  B. SUBS PC, LR-#4
  C. SUBS PC. LR, #6
  D. SUBS PC, LR, #8
  C. SUBS PC. LR, #6

• Question 149:

  Which of the following statements best describes a Board Support Package (BSP)?

  A. PC interface hardware for configuring a boot monitor
  B. Hardware specific source code needed for operating system support
  C. A working port of Linux for a specific hardware platform
  D. Debugging hardware and software supplied with a development board
  B. Hardware specific source code needed for operating system support

• Question 150:

  In an MPCore system, when one core is waiting for resources to be released, what instruction could be used to reduce that core's power consumption?

  A. WFE
  B. PLD
  C. NOP
  D. DSB
  A. WFE