ARM EN0-001 Online Practice Questions and Exam Preparation

ARM EN0-001 Online Questions & Answers

• Question 131:

  What is the value of R2 after execution of the following instruction sequence? MOV R3, #0xBA MOV R2/#0x10 BIC R2, R3, R2

  A. R2 = 0xBB
  B. R2 = 0xCB
  C. R2 = 0xAA
  D. R2 = 0xCC
  C. R2 = 0xAA

• Question 132:

  In which TWO of the following locations would a compiler typically place local variables? (Choose two)

  A. ROM
  B. Heap
  C. Cache
  D. Registers
  E. Stack
  D. Registers
  E. Stack

• Question 133:

  In a Cortex-A9 MPCore cluster with four processors, which of the processors can be interrupted by a software-generated interrupt?

  A. Any processor in the cluster
  B. Only the processor raising the software-generated interrupt
  C. Only processors outside the cluster
  D. Any processor except the one raising the software-generated interrupt
  A. Any processor in the cluster

• Question 134:

  Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

  How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

  A. 5 cycles
  B. 7 cycles
  C. 8 cycles
  D. 15 cycles
  B. 7 cycles

• Question 135:

  During an investigation into a software performance problem an engineer doubles the clock frequency of a cached ARM processor running the software. Unfortunately the performance of the application does not increase by very much, despite running on the processor for 100% of the time. What is likely to be the main bottleneck in the system?

  A. The processor is context switching between multiple processes
  B. Performance is limited by the speed of external memory
  C. The processor is taking too long to execute branch instructions
  D. The system is raising interrupts too fast for the processor to handle them
  B. Performance is limited by the speed of external memory

• Question 136:

  In a loop termination test, how might a programmer indicate to the compiler that the loop iteration count limit is divisible by four?

  A. AND the count limit with -0x3
  B. Add 4 to the count limit
  C. Subtract 4 from the count limit
  D. Shift the count limit left two bit positions
  A. AND the count limit with -0x3

• Question 137:

  LDREX and STREX were introduced in which ARM architecture version?

  A. ARMv5TE
  B. ARMv6
  C. ARMv6K
  D. ARMv7
  B. ARMv6

• Question 138:

  When using the default ARM tool-chain libraries for bare-metal applications. I/O functionality is rerouted and handled by a connected debugger. This is often referred to as semihosting. Which one of the following explanations BEST describes how this feature can be implemented by a debugger?

  A. The library directly sends I/O requests to the debugger using the JTAG connection
  B. While the target is running, the debugger processes I/O requests from a shared queue in memory
  C. The I/O library calls rely on an Ethernet connection to redirect the requests to the debugger
  D. The I/O library calls generate an exception that is trapped and handled by the debugger
  D. The I/O library calls generate an exception that is trapped and handled by the debugger

• Question 139:

  Which of the following sequences of stages comprise the ARM7TDMI three-stage pipeline?

  A. Fetch, Decode, Execute
  B. Decode, Fetch, Execute
  C. Execute, Fetch, Decode
  D. Fetch, Execute, Execute
  A. Fetch, Decode, Execute

• Question 140:

  When an interrupt service routine reads the Generic Interrupt Controller (GIC) Interrupt Acknowledge Register, what state transition occurs for that interrupt ID?

  A. Inactive to Active
  B. Inactive to Pending
  C. Active to Inactive
  D. Pending to Active
  D. Pending to Active