ARM EN0-001 Online Practice Questions and Exam Preparation

ARM EN0-001 Online Questions & Answers

• Question 111:

  To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?

  A. PC=LR
  B. PC=LR44
  C. PC=LR-4
  D. PC=LR-8
  D. PC=LR-8

• Question 112:

  The Cortex-A9 MPCore processor contains a hardware block whose function is to maintain data cache coherency between cores. What is the name of this block?

  A. Shareable Memory
  B. Snoop Control Unit
  C. Private Memory Region
  D. Level 2 Cache Controller
  B. Snoop Control Unit

• Question 113:

  When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?

  A. The linker
  B. The archiver
  C. The compiler
  D. The assembler
  A. The linker

• Question 114:

  Assume a Big-Endian (BE) memory system with the following memory contents. Byte Address Contents 0x100 0x11 0x101 0x22 0x102 0x33 0x103 0x44 If R5 = 0x100, what are the contents of R4 after performing the following operation? LDR R4, [R5]

  A. 0x11223344
  B. 0x44332211
  C. 0x22114433
  D. 0x33441122
  A. 0x11223344

• Question 115:

  Which ARMv7 instructions are recommended to implement a semaphore?

  A. SWP, SWPB
  B. TEQ, TST
  C. STC, SBC
  D. LDREX, STREX
  D. LDREX, STREX

• Question 116:

  According to the EABI. what would the C size of () operator return when given the following structure?

  

  A. 19
  B. 20
  C. 24
  D. 28
  C. 24

• Question 117:

  Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?

  A. Memory read instructions, and memory write instructions
  B. Architecturally executed instructions, and instruction fetches causing a cache line refill
  C. Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access
  D. Memory read or write operations causing a cache access, and architecturally executed instructions
  C. Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

• Question 118:

  Consider the following code sequence, executing on a processor which implements ARM Architecture v7-A.

  LDR r0, [r1]

  STR r0, [r2]

  STR r3, [r3]

  R1 points to a location in normal memory. R2 and R3 point to device memory.

  Which of the following statements best describes the ordering rules which apply to this sequence?

  A. The two writes to device memory will happen in program order, but the read can be performed out of order
  B. The memory accesses can happen in any order
  C. The memory accesses will happen in program order
  D. The read to r0 and the write from r0 will happen in program order, but the write from r3 can be performed out of order
  C. The memory accesses will happen in program order

• Question 119:

  Printf statements could be used to achieve which of the following debug tasks?

  A. Observe changes to a local variable in a function
  B. Capture a real-time trace of program execution
  C. Debug boot code, before a call to the C main() function
  D. Stop the processor at an interesting location in the code
  A. Observe changes to a local variable in a function

• Question 120:

  The interval of time from an external interrupt request signal being raised to the first fetch of an instruction of the interrupt handler is called the interrupt:

  A. Latency
  B. Priority
  C. Service thread
  D. Jitter
  A. Latency