ARM EN0-001 Online Practice Questions and Exam Preparation

ARM EN0-001 Online Questions & Answers

• Question 101:

  The Q-flag in the program status register (PSR) indicates which of the following?

  A. Arithmetic overflow has occurred
  B. Processor is in Thumb execution state
  C. Imprecise data aborts are currently disabled
  D. Saturation has occurred after execution of a saturated arithmetic instruction
  D. Saturation has occurred after execution of a saturated arithmetic instruction

• Question 102:

  On an ARM processor that does not implement Security Extensions, which one of the following can be the starting address of the exception vector table?

  A. 0xFFFFFFFF
  B. 0xFFFFFFF0
  C. 0xFFFF0000
  D. 0x0000FFFF
  C. 0xFFFF0000

• Question 103:

  Which TWO of the following interrupt types does a Generic Interrupt Controller (GIC) support? (Choose two)

  A. Interrupt from a private peripheral to a processor
  B. Interrupt from a processor to a private peripheral
  C. Interrupt from a shared peripheral to a processor
  D. Interrupt from a processor to a shared peripheral
  E. Interrupt from a private peripheral to a shared peripheral
  F. Interrupt from a shared peripheral to a private peripheral
  A. Interrupt from a private peripheral to a processor
  C. Interrupt from a shared peripheral to a processor

• Question 104:

  A C code segment contains three calls to a function, foobar ().

  This code segment is to be linked with a static library that defines foobar ().

  Ignoring inlining, how many copies of foobar () will the ARM linker place in the output?

  A. None
  B. Always one
  C. Always three
  D. One or more depending on optimization level
  B. Always one

• Question 105:

  In an operating system environment, most applications are executed in which processor mode?

  A. Supervisor
  B. IRQ
  C. System
  D. User
  D. User

• Question 106:

  Is it possible to use an interrupt controller based on the Generic Interrupt Controller (GIC) architecture in a device built around a single core Cortex-A9 MPCore processor?

  A. No, they are completely incompatible
  B. Yes, all Cortex-A9 MPCore processors include an integrated GIC
  C. Yes, but a dummy second processor has to be included
  D. No, a GIC is only compatible with multi-core Cortex-A9 processors
  B. Yes, all Cortex-A9 MPCore processors include an integrated GIC

• Question 107:

  Which TWO of the following accurately describe constraints on the location of the Tightly Coupled Memory (TCM) regions in a Cortex-R4 processor? (Choose two)

  A. TCM Region A (ATCM) must be at a lower memory address than TCM Region B (BTCM)
  B. TCM Region A can only be located at address 0x0
  C. Both TCM regions must be placed at addresses which are aligned to their size
  D. The two TCM regions may not overlap
  E. TCM Region B (BTCM) must be located immediately above TCM Region A (ATCM)
  C. Both TCM regions must be placed at addresses which are aligned to their size
  E. TCM Region B (BTCM) must be located immediately above TCM Region A (ATCM)

• Question 108:

  What are the values of the NZCV bits in the CPSR after executing the following instructions? LDR R0, = 0xFFFFFFFF ADDS R0, R0, #1

  A. 0101
  B. 0110
  C. 1001
  D. 1010
  B. 0110

• Question 109:

  An undefined instruction will cause an Undefined Instruction exception to be taken when:

  A. It is fetched.
  B. It is decoded.
  C. It is executed.
  D. It writes back its results.
  C. It is executed.

• Question 110:

  Using a Generic Interrupt Controller (GIC), when the interrupt handler writes to the End of Interrupt Register (ICCEOIR), which of the following state transitions might occur for that interrupt ID?

  A. Inactive to Active
  B. Pending to Active
  C. Active to Inactive
  D. Active to Pending
  C. Active to Inactive