ARM EN0-001 Online Practice Questions and Exam Preparation

ARM EN0-001 Online Questions & Answers

• Question 71:

  Within the ARMv7 architecture, which one of the following features is unique to the ARMv7-A profile?

  A. Cache support
  B. Privileged execution
  C. The ARM instruction set
  D. Virtual memory support
  D. Virtual memory support

• Question 72:

  In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?

  A. D0..D31 and S0..S31 are separate register banks
  B. D0..D31 overlap with S0..S63
  C. D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers
  D. D0 overlaps with S0, D1 with S1 etc. up to D31 and S31
  C. D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers

• Question 73:

  Which of the following is preserved in dormant mode?

  A. Core register contents
  B. CP15 (system) register settings
  C. Debug state
  D. Cache contents
  D. Cache contents

• Question 74:

  On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?

  A. This transition is not possible
  B. Execution of an SMC instruction
  C. Execution of an SMC instruction followed by an SVC instruction
  D. Execution of an SVC instruction followed by an SMC instruction
  D. Execution of an SVC instruction followed by an SMC instruction

• Question 75:

  Which of the following is an external exception?

  A. Supervisor Call
  B. FIQ
  C. Undefined Instruction
  D. Parity
  B. FIQ

• Question 76:

  Which of these instructions is a correct translation of the body of function f?

  struct T { char a; int b; };

  int f(struct T *p) { return p->b; }

  A. LDR r0, [r0], #1
  B. LDR r0, [r0]. #4
  C. LDR r0, [r0.#1]
  D. LDR r0, [r0. #4]
  D. LDR r0, [r0. #4]

• Question 77:

  Which one of these statements is TRUE about code running on final hardware without a debugger attached?

  A. It must start executing from RAM
  B. RAM must be initialized before reset
  C. Exception handlers must execute from ROM or flash memory
  D. It must not execute semihosting SVC or BKPT instructions
  D. It must not execute semihosting SVC or BKPT instructions

• Question 78:

  An external debugger would need to clean the contents of the processor data cache in which of the following cases?

  A. When it changes the contents of ARM registers (r0-r15)
  B. When it displays the contents of an area of cacheable data
  C. When it displays the contents of an area of cacheable code D. When it sets a software breakpoint
  D

• Question 79:

  How is data written into NOR flash memory?

  A. Data can only be written once, when the flash device is being manufactured
  B. Writing data to the memory locations using store instruction, as you would with RAM
  C. Reading and writing specific registers following a device-specific procedure
  D. Using an external programming device, which utilizes an ultra-violet lamp to alter the data stored on the device
  C. Reading and writing specific registers following a device-specific procedure

• Question 80:

  What is the maximum value of the immediate field in an ARM SVC instruction?

  A. 0x0
  B. 0xF
  C. 0xFF
  D. 0xFFFFFF
  D. 0xFFFFFF