ARM ARM Certifications EN0-001 Questions & Answers

• Question 61:

  Which of the following best describes the relationship between Tightly Coupled Memories (TCM), Level 1 (L1) and Level 2 (L2) cache memory systems?

  A. TCMs are a part of only L1 cache system

  B. TCMs are a part of only L2 cache system

  C. TCMs are part of both L1 and L2 cache systems

  D. TCMs are not part of either L1 or L2 cache systems

  Correct Answer: D

• Question 62:

  In Architecture ARMv7-A which one of the following has a known physical address at power-on reset?

  A. The exception vector table

  B. The Memory Management Unit (MMU) translation table

  C. The Stack Pointer (SP)

  D. The System Control Register (SCTLR)

  Correct Answer: A

• Question 63:

  When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?

  A. The linker

  B. The archiver

  C. The compiler

  D. The assembler

  Correct Answer: A

• Question 64:

  LDREX and STREX were introduced in which ARM architecture version?

  A. ARMv5TE

  B. ARMv6

  C. ARMv6K

  D. ARMv7

  Correct Answer: B

• Question 65:

  The ARMv7-A virtual memory management system supports 32-bit (short) and 64-bit (long) page table descriptors. The sizes of a small page in a short descriptor and a small page in a long descriptor are:

  A. 1 KB and 4KB respectively

  B. 4KB and 4KB respectively

  C. 4KB and 16KB respectively

  D. 16KB and 16KB respectively

  Correct Answer: B

• Question 66:

  An external debugger would need to clean the contents of the processor data cache in which of the following cases?

  A. When it changes the contents of ARM registers (r0-r15)

  B. When it displays the contents of an area of cacheable data

  C. When it displays the contents of an area of cacheable code

  D. When it sets a software breakpoint

  Correct Answer: D

• Question 67:

  A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes. How many bits are required to index a cache line in a way?

  A. 6 bits

  B. 7 bits

  C. 9 bits

  D. 15 bits

  Correct Answer: B

• Question 68:

  When developing a product using the standard ARM C library, what is the minimum effort required to re-target all platform-specific functions in the library?

  A. Replace all functions which use semi-hosting

  B. Locate the stack in an area of RAM

  C. Set the locale variable appropriately

  D. All functions in the standard library must be rewritten

  Correct Answer: A

• Question 69:

  In a system using the Security Extensions, how does the Secure Monitor execute a switch from Secure to Non-secure state?

  A. Encrypts Secure register contents, sets the NS bit in SCTLR and branches directly to Normal world code

  B. Saves Secure register contents, sets all registers to zero, sets the NS bit in SCTLR and branches directly to Normal world code

  C. Saves Secure register contents, loads Non-secure ones from memory, sets the NS bit in SCTLR and performs an exception return

  D. Sets the NS bit in SCTLR and performs an exception return - all registers are banked in hardware and switched automatically

  Correct Answer: C

• Question 70:

  Processors which implement the ARMv7-A architecture can be configured to allow unaligned memory access. Unaligned accesses have a number of advantages, disadvantages, and limitations.

  Which TWO of the following statements are true? (Choose two)

  A. Unaligned accesses may take more cycles to execute than aligned accesses

  B. Unaligned loads and stores are necessary for accessing fields in packed structures

  C. A program compiled using unaligned accesses can be safely executed on all ARMv7-A devices

  D. If the relevant control register setting is enabled all loads and stores can function from unaligned addresses

  E. Unaligned accesses can only be made to Normal memory

  Correct Answer: AE