ARM ARM Certifications EN0-001 Questions & Answers

• Question 191:

  Using a lower optimization level when compiling will:

  A. Produce faster code.

  B. Produce smaller code.

  C. Produce non standard-compliant code.

  D. Produce code that might be easier to debug.

  Correct Answer: D

• Question 192:

  Which instruction would be used to return from a Reset exception?

  A. MOVS PC, R14

  B. MOVSPC, R13

  C. Architecturally not defined

  D. SUBS PC, R14, #4

  Correct Answer: C

• Question 193:

  In a Cortex-A9 MPCore cluster with four processors, which of the processors can be interrupted by a software-generated interrupt?

  A. Any processor in the cluster

  B. Only the processor raising the software-generated interrupt

  C. Only processors outside the cluster

  D. Any processor except the one raising the software-generated interrupt

  Correct Answer: A

• Question 194:

  To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?

  A. PC=LR

  B. PC=LR44

  C. PC=LR-4

  D. PC=LR-8

  Correct Answer: D

• Question 195:

  Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?

  A. R0=0x100, R1 =0x1000

  B. R0=0x100, R1=0x1002

  C. R0=0x101, R1=0x1002

  D. R0=0x101. R1=0x1003

  Correct Answer: D

• Question 196:

  Which ARMv7 instructions are recommended to implement a semaphore?

  A. SWP, SWPB

  B. TEQ, TST

  C. STC, SBC

  D. LDREX, STREX

  Correct Answer: D

• Question 197:

  Within the ARMv7 architecture, which one of the following features is unique to the ARMv7-A profile?

  A. Cache support

  B. Privileged execution

  C. The ARM instruction set

  D. Virtual memory support

  Correct Answer: D

• Question 198:

  When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?

  int foo( int arg_a, int arg_b, int arg_c )

  A. 0

  B. 4

  C. 8

  D. 12

  Correct Answer: A

• Question 199:

  The following pseudocode sequence shows a flag being set to indicate that new data is ready to be read by another thread:

  data = 123;

  ready = true;

  Assuming that the reader threads may execute on any other core of a multicore system, which of the following is the most efficient memory barrier to place between the two writes to prevent them being observed in the opposite order?

  A. DSBSY

  B. DSBST

  C. DMBSY

  D. DMBST

  Correct Answer: D

• Question 200:

  On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?

  A. This transition is not possible

  B. Execution of an SMC instruction

  C. Execution of an SMC instruction followed by an SVC instruction

  D. Execution of an SVC instruction followed by an SMC instruction

  Correct Answer: D