Which of the following would enable the use of a symmetric multiprocessing (SMP) operating system?
A. A dual-core Cortex-A9 processor
B. A Cortex-R4 processor with a Cortex-M3 system controller
C. A Cortex-A8 processor with a graphics processing unit (GPU)
D. A uni-core Cortex-A5 processor with a digital signal processor (DSP)
What will be the contents of R2 after the execution of the following piece of code? LDRR1, =0xAABBCCDD MOV R2, #0x4 ANDSR1, R1, #0x4 ADDNE R2, R2, #0x4
A. R2 = 0x4
B. R2 = 0x8
C. R2 = 0xAABBCCDD
D. R2 = 0xAABBCCD4
Which of the following statements regarding Strongly-ordered memory is architecturally FALSE?
A. Address locations marked as Strongly-ordered memory are never held in a cache
B. The architecture does not permit speculative data accesses to Strongly-ordered memory
C. A write to Strongly-ordered memory is permitted to complete before it reaches the peripheral or memory component accessed by the write
D. The number and size of accesses to Strongly-ordered memory must be the same as that specified by the program
Cross compiling enables a programmer to:
A. Produce a binary object that will run on processors based on any architecture.
B. Mix different source languages within the same source file and compile with a single tool.
C. Run code written for one processor on a processor based on a different architecture.
D. Compile target code using a computer based on a different architecture.
Which of the following functions can be performed by a spinlock?
A. Encrypting sensitive data on a network
B. Preventing interrupts from being received by a CPU
C. Preventing unauthorized access to an ARM powered device
D. Protecting a critical section or data structure from concurrent access
In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?
A. D0..D31 and S0..S31 are separate register banks
B. D0..D31 overlap with S0..S63
C. D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers
D. D0 overlaps with S0, D1 with S1 etc. up to D31 and S31
As part of the ABI specification, the AAPCS defines which of the following?
A. How many levels of nested function calls are permitted on ARM systems
B. How to measure the maximum amount of stack required by an application
C. On which mode's stack you need to save the return address in a non-leaf function
D. Which registers need to be preserved by a function
Which of the following statements is TRUE with respect to the power consumption related to memory accesses?
A. Accessing a large memory device consumes less power than accessing a small one
B. A series of non-sequential accesses is more efficient than a series of sequential accesses
C. Increasing the size of the cache will always reduce power consumption for a given application
D. Storing frequently used data in Tightly Coupled Memory will reduce power consumption
On an ARM processor that does not implement Security Extensions, which one of the following can be the starting address of the exception vector table?
A. 0xFFFFFFFF
B. 0xFFFFFFF0
C. 0xFFFF0000
D. 0x0000FFFF
Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.
How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?
A. 5 cycles
B. 7 cycles
C. 8 cycles
D. 15 cycles
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