ARM ARM Certifications EN0-001 Questions & Answers

• Question 201:

  What architecture does the ARM11 MPCore implement?

  A. ARMv6

  B. ARMv6K

  C. ARMv7-A

  D. ARMv7-A with the Multiprocessing Extensions

  Correct Answer: B

• Question 202:

  The following function is declared: float func(float fl, float f2);

  The file file1 .c contains a call to func, and is compiled with hard floating point linkage. The file file2.c contains the definition of func, and is compiled with AACPS soft floating point linkage.

  Assume that the two files are successfully linked using the ARM linker and an executable is generated. The generated executable:

  A. Exhibits correct behavior, but suffers a performance penalty because the linker has to generate extra code.

  B. Exhibits correct behavior, and suffers no performance penalty.

  C. Will not execute.

  D. Exhibits incorrect behavior.

  Correct Answer: D

• Question 203:

  During an investigation into a software performance problem an engineer doubles the clock frequency of a cached ARM processor running the software. Unfortunately the performance of the application does not increase by very much, despite running on the processor for 100% of the time. What is likely to be the main bottleneck in the system?

  A. The processor is context switching between multiple processes

  B. Performance is limited by the speed of external memory

  C. The processor is taking too long to execute branch instructions

  D. The system is raising interrupts too fast for the processor to handle them

  Correct Answer: B

• Question 204:

  In which of the following situations would you use a mutex to avoid synchronization problems?

  A. A single-threaded application needs to manage two separate UART peripherals

  B. Two independent threads running on a single processor both need to access a single UART

  C. In a dual-core system, a UART is accessed by a single thread running on one of the processors

  D. In a dual-core system, processor A needs to access UART A and processor B needs to access UART B

  Correct Answer: B

• Question 205:

  Which of the following will cause the ARM Compiler to target the Thumb instruction set?

  A. Compiling exception handlers

  B. Specifying a Thumb-capable processor (e.g. -cpu=Cortex-A9)

  C. Enabling Thumb code generation on the command line (--thumb)

  D. Configuring the compiler for maximum code density (-Ospace)

  Correct Answer: C

• Question 206:

  Which TWO of the following options can the ARM Compiler (armcc) directive__packed be used for? (Choose two)

  A. To tell the compiler to use only Thumb code

  B. To tell the compiler to produce code of minimum size

  C. To tell the compiler to use the v6 SIMD pack/unpack instructions

  D. To tell the compiler that an object can be on an unaligned address

  E. To tell the compiler not to perform padding inside structures

  Correct Answer: DE

• Question 207:

  When using an Operating System, which of the following operations can NOT typically be done by user processes?

  A. Reading the link register (R14)

  B. Reading data from the user stack

  C. Changing from ARM state to Thumb state

  D. Changing the interrupt mask bits (A, I, F) in the CPSR

  Correct Answer: D

• Question 208:

  In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?

  A. ±32MB

  B. ±4MB

  C. ±12KB

  D. ±4KB

  Correct Answer: A

• Question 209:

  Which of the following ARM processors has the best energy efficiency (measured in mW/MHz)?

  A. Cortex-M0+

  B. Cortex-M4

  C. Cortex-R4

  D. Cortex-A15

  Correct Answer: A

• Question 210:

  In an ARMv7-A processor with Security Extensions, which of the following mechanisms best describes the way Secure memory is protected from access by software running in a Non-secure privileged mode?

  A. The memory system has visibility of the security status of all accesses, and will reject all Non- secure accesses to Secure memory

  B. Secure memory contents are encrypted, and cannot be decrypted by Non-secure software

  C. The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set

  D. The MMU generates an abort on accesses to Secure memory performed by Non-secure software

  Correct Answer: A