ARM ARM Certifications EN0-001 Questions & Answers

• Question 41:

  In an operating system environment, most applications are executed in which processor mode?

  A. Supervisor

  B. IRQ

  C. System

  D. User

  Correct Answer: D

• Question 42:

  Which of the following is an advantage of the single-step debug technique?

  A. It allows a complete trace of real-time program execution to be captured

  B. It reduces the number of pins required to connect the debugger to the processor

  C. It allows examination of the system state before and after execution of a statement

  D. It requires only one change to the program source code

  Correct Answer: C

• Question 43:

  Which of the following is an external exception?

  A. Supervisor Call

  B. FIQ

  C. Undefined Instruction

  D. Parity

  Correct Answer: B

• Question 44:

  An ARM processor connected to a Generic Interrupt Controller (GIC) is handling an active interrupt 11. A new interrupt 12 that is received at the GIC is forwarded to the processor, and the active interrupt 11 is preempted. Which of the following possible values of 11's priority (P1), 12's priority (P2) and the processor's priority mask (PM) permit this to happen? Assume there are 256 priority levels implemented.

  A. P1 = 0x0F, P2 = 0x10, PM = 0xFF

  B. P1 = 0x10, P2 = 0x0F, PM = 0xFF

  C. P1 =0x0F, P2 = 0x10. PM = 0x0

  D. P1 = 0x10, P2 = 0x0F, PM = 0x0

  Correct Answer: B

• Question 45:

  Which of these items is typically shared between threads running in the same Operating System (OS) process?

  A. Stack

  B. Memory map

  C. Register values

  D. Program Counter

  Correct Answer: B

• Question 46:

  Assume a Big-Endian (BE) memory system with the following memory contents. Byte Address Contents 0x100 0x11 0x101 0x22 0x102 0x33 0x103 0x44 If R5 = 0x100, what are the contents of R4 after performing the following operation? LDR R4, [R5]

  A. 0x11223344

  B. 0x44332211

  C. 0x22114433

  D. 0x33441122

  Correct Answer: A

• Question 47:

  Which of the following features was added in version 2 of the ARM Architecture Advanced SIMD extensions?

  A. Additional quadword registers

  B. Support for double precision floating-point arithmetic

  C. Fused Multiply-Accumulate (Fused MAC) instructions

  D. Support for polynomials

  Correct Answer: C

• Question 48:

  Which THREE of the following items should be preserved by software when entering dormant mode? (Choose three)

  A. Current Program Status Register (CPSR)

  B. Contents of the Level 2 data cache

  C. The Floating Point Status and Control Register (FPSCR)

  D. All User mode general-purpose registers

  E. The CP15 Multiprocessor Affinity Register

  F. Contents of the Level 1 data cache

  Correct Answer: ACD

• Question 49:

  When should an ISB instruction be used?

  A. When executing a long branch

  B. When clearing the branch predictor caches

  C. When reading a register from a coprocessor

  D. When returning from an exception handler

  Correct Answer: B

• Question 50:

  When the software floating point emulation library is used, how will the parameters be passed to the following function?

  void foo(float f1, float f2, float f3, float f4);

  A. On the stack

  B. In registers s0-s3

  C. In registers d0-d3

  D. In registers r0-r3

  Correct Answer: D