ARM ARM Certifications EN0-001 Questions & Answers

• Question 31:

  Clicking the Start button in a debugger:

  A. Begins processor execution.

  B. Resets the processors.

  C. Erases existing breakpoints.

  D. Puts the processor(s) into debug state.

  Correct Answer: A

• Question 32:

  Which of the following ARM processors has a superscalar micro architecture?

  A. ARM926EJ-S

  B. Cortex-M0

  C. Cortex-M3

  D. Cortex-A8

  Correct Answer: D

• Question 33:

  When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?

  A. Writes dirty data cache lines to memory

  B. Reloads dirty data cache lines from memory

  C. Speculatively preloads data into the cache

  D. Writes dirty data cache lines to memory and marks those lines as invalid

  Correct Answer: A

• Question 34:

  In an ARMv7 processor that includes the Advanced SIMD (NEON) extension, how many single precision floating point values can be stored in the Q0 register?

  A. 1

  B. 2

  C. 4

  D. 8

  Correct Answer: C

• Question 35:

  Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?

  A. An external DMA engine modifies data in a region of data memory which is already cached by the processor

  B. An external agent needs to read data which has been modified by the processor in a cacheable memory region

  C. Debugger reads data from a shared, cacheable memory location

  D. One core modifies data in a shared cacheable memory region

  Correct Answer: B

• Question 36:

  The Q-flag in the program status register (PSR) indicates which of the following?

  A. Arithmetic overflow has occurred

  B. Processor is in Thumb execution state

  C. Imprecise data aborts are currently disabled

  D. Saturation has occurred after execution of a saturated arithmetic instruction

  Correct Answer: D

• Question 37:

  Which one of the following statements best describes the function of vector catch logic?

  A. It traps writes to the memory containing the vector table

  B. It provides additional resources for debugging exception handlers

  C. It provides configurable exception priorities on an ARM processor

  D. It provides an improved mechanism for an application to handle exceptions

  Correct Answer: B

• Question 38:

  When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)

  A. Coherency management between all L1 data caches

  B. Broadcast of some inner-shared cache and TLB maintenance operations

  C. Broadcast of some outer-shared cache and TLB maintenance operations

  D. Coherency management between all L1 instruction caches

  E. Coherency management between all external caches

  Correct Answer: AB

• Question 39:

  Which one of these statements is TRUE about code running on final hardware without a debugger attached?

  A. FIQ exceptions must not be taken

  B. The instruction cache must be enabled

  C. Global variables must be initialized to zero

  D. The Reset Vector must reside in non-volatile memory

  Correct Answer: D

• Question 40:

  Optimizing for space will:

  A. Produce an image which is decompressed at run-time.

  B. Cause the compiler to unroll loops where possible.

  C. Result in more functions being inlined by the compiler.

  D. Produce smaller code, even if this results in slower execution.

  Correct Answer: D