ARM ARM Certifications EN0-001 Questions & Answers

• Question 101:

  A C code segment contains three calls to a function, foobar ().

  This code segment is to be linked with a static library that defines foobar ().

  Ignoring inlining, how many copies of foobar () will the ARM linker place in the output?

  A. None

  B. Always one

  C. Always three

  D. One or more depending on optimization level

  Correct Answer: B

• Question 102:

  In which of the following scenarios would cache maintenance operations be necessary in an ARMv7 system?

  A. Before executing code that uses the NEON instruction set

  B. Before handling an interrupt request raised by an external device

  C. Before checking the status of a semaphore

  D. Before reading cacheable memory that has been written to by an external bus master

  Correct Answer: D

• Question 103:

  The size of a C 'int' type in the ARM architecture is:

  A. 8 bits

  B. 16 bits

  C. 32 bits

  D. 64 bits

  Correct Answer: C

• Question 104:

  In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:

  -

  CPU 0 and 1 are sleeping in low-power state following a WFI instruction.

  -

  CPU 2 is executing program code.

  -

  CPU 3 is sleeping in low-power state following a WFE instruction. CPU 2 executes a SEV instruction. What is the effect on the system?

  A.

  CPU 0: executing, CPU 1: executing, CPU 2: executing. CPU 3: executing

  B.

  CPU 0: executing, CPU 1: executing. CPU 2: executing. CPU 3: sleeping

  C.

  CPU 0: sleeping, CPU 1: sleeping. CPU 2: executing. CPU 3: executing

  D.

  CPU 0: sleeping, CPU 1: sleeping. CPU 2: sleeping, CPU 3: executing

  Correct Answer: C

• Question 105:

  In which TWO of the following locations would a compiler typically place local variables? (Choose two)

  A. ROM

  B. Heap

  C. Cache

  D. Registers

  E. Stack

  Correct Answer: DE

• Question 106:

  An embedded application running on an ARM processor is not meeting its expected performance target. The target hardware on which the application is running allows the frequency of the CPU to be increased independently from the memory system.

  The CPU frequency is increased from 800 MHz to 1 GHz and experiments verify that the application performance does not increase.

  Which one of the following statements MUST BE TRUE?

  A. The performance is limited by something other than the CPU

  B. The cache hit rate has gone down

  C. The measurement methodology is flawed and the experiment needs to be repeated

  D. The operating system is performing more context switches

  Correct Answer: A

• Question 107:

  In a Cortex-A9 processor, CP14 system control registers are used for:

  A. Cache control operations

  B. Address translation operations

  C. Debug control and status information

  D. Architecture feature ID registers

  Correct Answer: C

• Question 108:

  When using a Generic Interrupt Controller (GIC), how does code cause a software-generated interrupt?

  A. By executing an SGI instruction

  B. By writing to a register in the GIC

  C. By writing to the F bit in the CPSR

  D. By writing to the I bit in the CPSR

  Correct Answer: B

• Question 109:

  In a hardware system that runs software providing secure systems, which of the following describes the behavior of external memory and peripherals?

  A. They are not accessible when the processor is in Non-secure state

  B. They cannot know whether the processor is performing a Secure or Non-secure access

  C. They can use the Secure or Non-secure status of the access to decide what response to give

  D. They are required to give an ERROR response when Secure code accesses Non-secure locations in memory

  Correct Answer: C

• Question 110:

  In a symmetric multi-processing (SMP) software architecture, which of the following pairs of statements are TRUE? (Select the option in which BOTH statements are TRUE).

  A. The roles of individual cores are determined dynamically. Each core has its own set of external peripherals.

  B. Each core has the same view of memory and shared peripherals. Any user application, process or task can be scheduled to run on any core.

  C. The roles of individual cores are statically determined by the system designer. Hardware must be implemented to provide cache coherency between the cores.

  D. Each core has the same view of memory and peripherals. The roles of individual cores are statically determined by the system designer.

  Correct Answer: B