ARM ARM Certifications EN0-001 Questions & Answers

• Question 111:

  The instruction LDR pc, [ r1 ] takes longer to execute on a particular system, than the instruction LDR r0, [ r1 ]. In both cases, r1 points to the same address in external memory.

  Which of the following is the most likely explanation of why it takes more cycles?

  A. The value read from address r1 must be passed from the data side of the processor to the instruction side

  B. The LDR pc, [r1] causes the instruction pipeline to be flushed, but the LDR r0, [r1] does not

  C. The LDR pc, [ r1 ] instruction requires additional alignment checking, as the result must be half word-aligned (Thumb) or word-aligned (ARM)

  D. The LDR r0, [r1] can be speculatively executed, but the LDR pc, [r1] instruction cannot be speculatively executed

  Correct Answer: B

• Question 112:

  Which one of these statements is TRUE about code running on final hardware without a debugger attached?

  A. It must start executing from RAM

  B. RAM must be initialized before reset

  C. Exception handlers must execute from ROM or flash memory

  D. It must not execute semihosting SVC or BKPT instructions

  Correct Answer: D

• Question 113:

  Which of these processors is only available as a single core configuration?

  A. Cortex-A5

  B. Cortex-A8

  C. Cortex-A9

  D. Cortex-A15

  Correct Answer: B

• Question 114:

  When using the Performance Monitoring Unit to count runtime events the counter registers are limited to 32-bits. How can more than 2A32 events be counted without significantly impacting the software performance?

  A. Register an interrupt which is triggered when the counter overflows

  B. Count the events using a 64-bit VFP register

  C. Allow one event type to use concatenated counter registers

  D. Poll the event counter, resetting it when the counter is close to overflowing

  Correct Answer: A

• Question 115:

  According to the EABI. what would the C size of () operator return when given the following structure?

  

  A. 19

  B. 20

  C. 24

  D. 28

  Correct Answer: C

• Question 116:

  When timing a critical function for an algorithm, using platform time functions such as get time of day (), the result is unpredictable; there is significant variance in the measured time between different runs of the benchmark. Which of the following strategies would improve the accuracy of the measurement?

  A. Time multiple executions of the algorithm and average the result

  B. Break the algorithm into smaller pieces and time them individually

  C. Run the code on a software model of the platform and collect the results on that system

  D. Add some code with a known overhead to the algorithm to make it run slower, and remove the overhead afterwards

  Correct Answer: A

• Question 117:

  Literal pool loads to access constants at run-time can be minimized by:

  A. Ensuring constants can be encoded as immediates in the current instruction set.

  B. Storing the code in ROM.

  C. Using Thumb code rather than ARM code.

  D. Compiling and linking as position-independent code.

  Correct Answer: A

• Question 118:

  Which of these instructions is a correct translation of the body of function f?

  struct T { char a; int b; };

  int f(struct T *p) { return p->b; }

  A. LDR r0, [r0], #1

  B. LDR r0, [r0]. #4

  C. LDR r0, [r0.#1]

  D. LDR r0, [r0. #4]

  Correct Answer: D

• Question 119:

  What type of debug point would you set when debugging flash memory or ROM?

  A. Start point

  B. Step point

  C. Hardware breakpoint

  D. Software breakpoint

  Correct Answer: B

• Question 120:

  Which one of the following statements is TRUE for monitor mode debugging?

  A. Monitor mode debug might be suitable for debugging timing critical control software

  B. Monitor mode debug only supports hardware breakpoints and watchpoints

  C. Monitor mode debug can be used to halt instruction execution on the processor

  D. Monitor mode debug is only available for ARM processors with a JTAG debug port

  Correct Answer: A