ARM ARM Certifications EN0-001 Questions & Answers

• Question 91:

  What type of instruction is used for cache maintenance operations?

  A. Dedicated ARM instructions

  B. Dedicated Thumb instructions

  C. CP14 instructions

  D. CP15 instructions

  Correct Answer: D

• Question 92:

  For Cortex-A series cores, what instruction(s) are recommended to implement a mutex or semaphore?

  A. SWP and SWPB

  B. DSB and ISB

  C. LDREX and STREX

  D. DMB

  Correct Answer: C

• Question 93:

  An undefined instruction will cause an Undefined Instruction exception to be taken when:

  A. It is fetched.

  B. It is decoded.

  C. It is executed.

  D. It writes back its results.

  Correct Answer: C

• Question 94:

  In Thumb state an ARMv7-A processor can execute:

  A. Only 16-bit Thumb instructions.

  B. Only 32-bit Thumb instructions.

  C. 16-bit and 32-bit Thumb instructions.

  D. 32-bit Thumb and certain ARM instructions.

  Correct Answer: C

• Question 95:

  If a Generic Interrupt Controller (GIC) implements 64 priority levels, which priority field bits hold the priority value?

  A. bits [5:0]

  B. bits [7:2]

  C. bits [15:10]

  D. bits [31:26]

  Correct Answer: B

• Question 96:

  What are the values of the NZCV bits in the CPSR after executing the following instructions? LDR R0, = 0xFFFFFFFF

  ADDS R0, R0, #1

  A. 0101

  B. 0110

  C. 1001

  D. 1010

  Correct Answer: B

• Question 97:

  What debugger view can you use to determine which function caused an exception?

  A. The Memory view

  B. The Variables view

  C. The Call Stack view

  D. The Breakpoint view

  Correct Answer: C

• Question 98:

  The following C function is compiled with hard floating point linkage.

  float function(int a, float b, int c, float d);

  Which register is used to pass argument c?

  A. R0

  B. R1

  C. R2

  D. R3

  Correct Answer: B

• Question 99:

  Which power mode describes the state where the ARM processor is powered down, but its Level 1 caches remain powered?

  A. Run mode

  B. Dormant mode

  C. Standby mode

  D. Shutdown mode

  Correct Answer: B

• Question 100:

  A deeply embedded real-time industrial control system is missing some hard real-time interrupt deadlines. Which of the following performance analysis techniques is the most suitable for identifying which routines are causing the problem?

  A. Use an ETM instruction trace profiler, which outputs information about the program as it runs

  B. Add some serial logging to the software, which outputs information about the program as it runs

  C. Add a new interrupt handler, which is triggered off a timer, and dump information about the interrupted process

  D. Use a JTAG sample-based profiler, which periodically halts the CPU, and dumps information about the interrupted process

  Correct Answer: A