ARM ARM Certifications EN0-001 Questions & Answers

• Question 21:

  Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)

  A. Thumb is a hybrid 16/32-bit instruction set

  B. No Thumb instructions can be conditionally executed

  C. Thumb code is always slower than the equivalent ARM code

  D. Some routines take more instructions in Thumb code than in the equivalent ARM code

  E. The Thumb instruction set can access the Advanced SIMD "NEON" instructions

  F. Thumb code is always more power-efficient than equivalent ARM code

  Correct Answer: ADE

• Question 22:

  Which of the following pairs of statements about the difference between a Memory Management Unit (MMU) and a Memory Protection Unit (MPU) is correct?

  A. The MMU uses translation tables. The MPU does not use translation tables.

  B. The MMU uses only physical addresses. The MPU translates virtual addresses to physical addresses.

  C. The MMU defines cacheability attributes for memory. The MPU does not define cacheability attributes for memory.

  D. The MMU defines access permissions for memory. The MPU does not define access permissions for regions of memory.

  Correct Answer: A

• Question 23:

  When a linker is removing unused sections during a static link (for example, -remove or -gc- sections), it finds the sections to keep by following all relocations starting from:

  A. The entry point(s).

  B. The function named 'main'.

  C. All local functions and variables.

  D. The reset vector.

  Correct Answer: A

• Question 24:

  Consider the following piece of code:

  

  The value of r7 after execution of the above piece of code is:

  A. 0xAA.

  B. 0x00.

  C. 0xBB.

  D. Unpredictable.

  Correct Answer: A

• Question 25:

  Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?

  A. Memory read instructions, and memory write instructions

  B. Architecturally executed instructions, and instruction fetches causing a cache line refill

  C. Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

  D. Memory read or write operations causing a cache access, and architecturally executed instructions

  Correct Answer: C

• Question 26:

  If a 16-bit Thumb instruction causes a Data Abort, which instruction would return from the handler to the instruction after the one that caused the data abort?

  A. SUBS PC. LR

  B. SUBS PC, LR-#4

  C. SUBS PC. LR, #6

  D. SUBS PC, LR, #8

  Correct Answer: C

• Question 27:

  Which of the following is an optional extension to the ARMv7-A architecture?

  A. VFP

  B. The System Control Coprocessor (CP15)

  C. Support for memory barriers

  D. A Memory Protection Unit conforming to the PMSA

  Correct Answer: A

• Question 28:

  According to the AAPCS, how many bytes are used to store a C variable of type 'int' in memory?

  A. 1 byte

  B. 2 bytes

  C. 4 bytes

  D. 8 bytes

  Correct Answer: C

• Question 29:

  The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

  A. Cache Size

  B. Clock Speed

  C. Program size

  D. Numbers of instructions executed

  Correct Answer: D

• Question 30:

  The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?

  A. Hard floating-point linkage

  B. Soft floating-point linkage without floating-point hardware

  C. Hard floating-point linkage with optimization for space

  D. Soft floating-point linkage with floating-point hardware

  Correct Answer: B