ARM ARM Certifications EN0-001 Questions & Answers

• Question 151:

  In an ARMv7-A processor, which control register is used to enable the Memory Management Unit (MMU)?

  A. The ACTLR

  B. The SCTLR

  C. The TTBCR

  D. The CONTEXTIDR

  Correct Answer: B

• Question 152:

  A simple method of measuring the performance of an application is to record the execution time using the clock on the wall or a wristwatch.

  When is this method INAPPROPRIATE?

  A. When executing the software using a simulation model

  B. When the processor is a Cortex-R4

  C. When instruction tracing is enabled

  D. When the processor is not executing instructions from cache

  Correct Answer: A

• Question 153:

  Consider the following code sequence, executing on a processor which implements ARM Architecture v7

  A.

  LDR r0, [r1]

  STR r0, [r2]

  STR r3, [r3]

  R1 points to a location in normal memory. R2 and R3 point to device memory.

  Which of the following statements best describes the ordering rules which apply to this sequence?

  A. The two writes to device memory will happen in program order, but the read can be performed out of order

  B. The memory accesses can happen in any order

  C. The memory accesses will happen in program order

  D. The read to r0 and the write from r0 will happen in program order, but the write from r3 can be performed out of order

  Correct Answer: C

• Question 154:

  When using the default ARM tool-chain libraries for bare-metal applications. I/O functionality is rerouted and handled by a connected debugger. This is often referred to as semihosting. Which one of the following explanations BEST describes how this feature can be implemented by a debugger?

  A. The library directly sends I/O requests to the debugger using the JTAG connection

  B. While the target is running, the debugger processes I/O requests from a shared queue in memory

  C. The I/O library calls rely on an Ethernet connection to redirect the requests to the debugger

  D. The I/O library calls generate an exception that is trapped and handled by the debugger

  Correct Answer: D

• Question 155:

  The Cortex-A9 processor implements a feature called "small loop mode" which reduces power consumption when executing small loops by turning off instruction cache accesses. Which of the following statements describes a condition that must be satisfied for this mode to be enabled?

  A. The loop must fit into two cache lines

  B. The loop must only contain forward branches

  C. Only integer arithmetic can be used

  D. All variables must be held in registers

  Correct Answer: A

• Question 156:

  Which is the best power saving mode to use while waiting to obtain a lock on a semaphore?

  A. Dormant

  B. Standby

  C. Shutdown

  D. Deep sleep

  Correct Answer: B

• Question 157:

  Which privileged mode can kernel code use to get direct access to the User mode registers R13 and R14?

  A. Abort mode

  B. System mode

  C. Hypeivisor mode

  D. Supervisor mode

  Correct Answer: B

• Question 158:

  An Advanced SIMD intrinsic has the prototype: int16x4_t vmul_n_s16(int16x4_t a, int16_t b); How many multiplications does this intrinsic compute?

  A. 1 multiplication

  B. 4 multiplications

  C. 16 multiplications

  D. 64 multiplications

  Correct Answer: B

• Question 159:

  Which of the following memory attributes, specified in a translation table entry, could be used to protect a page containing a read-sensitive peripheral from speculative instruction fetches?

  A. S (Secure)

  B. nG (non-Global)

  C. xN (Execute Never)

  D. AP (Access Permission)

  Correct Answer: C

• Question 160:

  An ARMv7 implementation might include the VFPv4-D32 floating point extension. What does the '32' indicate?

  A. The width of the datapath in bits

  B. The number of double precision floating point registers implemented

  C. The number of bits of data that can be loaded or stored at once

  D. The number of integer operations that can be performed simultaneously

  Correct Answer: B