It is common to declare structures as "packed" in order to minimize data memory size. Which of the following accurately describes the effect of this?
A. Members will be stored as bit-fields
B. Data Aborts will be disabled for all structure accesses
C. Structure members will be re-ordered so that the smallest are first
D. Multi-byte members are not required to be naturally aligned
When debugging an embedded Linux system, which one of the following techniques can be used to halt a single user thread, while allowing other threads to continue to run during the debug process?
A. Halting a single user thread in an embedded Linux system is not possible
B. Use the Linux kernel printk() function to output messages to the console
C. Connect a Linux-aware JTAG debugger to the target, which allows single-stepping of the code
D. Connect a debugger running on an external host device to an instance of gdbserver running on the target, using Ethernet
Which of the following processors includes a Generic Interrupt Controller as a standard component?
A. Cortex-A8
B. Cortex-M3
C. Cortex-R4F
D. Cortex-A9 MPCore
Assume a multicore processor with coherency management based on the MESI protocol. When a core changes the contents of a shared cache line, what is the final status of that line in the local cache?
A. Modified
B. Exclusive
C. Shared
D. Invalid
How is data written into NOR flash memory?
A. Data can only be written once, when the flash device is being manufactured
B. Writing data to the memory locations using store instruction, as you would with RAM C. Reading and writing specific registers following a device-specific procedure
D. Using an external programming device, which utilizes an ultra-violet lamp to alter the data stored on the device
Under which of the following data-sharing scenarios would cache maintenance operations be necessary?
A. Sharing data with another thread running on the same core
B. Sharing data with another process running on the same core
C. Sharing data with an external device
D. Sharing data with another CPU in an SMP system
A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?
A. Instruction cache clean only
B. Instruction cache invalidate only
C. Data cache clean and instruction cache invalidate
D. Data cache invalidate and instruction cache invalidate
Which of the following statements best describes a Board Support Package (BSP)?
A. PC interface hardware for configuring a boot monitor
B. Hardware specific source code needed for operating system support
C. A working port of Linux for a specific hardware platform
D. Debugging hardware and software supplied with a development board
In the Generic Interrupt Controller (GIC) architecture, which of the following ID numbers are reserved for interrupts that are private to a CPU interface?
A. ID0-ID7
B. ID0-ID15
C. ID0-ID31
D. ID0-ID63
What is the value of r0 after executing the following instruction sequence?
MOV r0, #200
MOV r5, #1
STR r3, [r0, r5, LSL#3]!
A. 200
B. 201
C. 204
D. 208
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