EN0-001 Web TestEngine demo

Exit VCEDump EN0-001 ARM Accredited Engineer
Question 28 of 32
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Q28 Single choice

Consider the following instruction sequence:

STR r0, [r2] ; instruction A

DSB

ADD r0, r1, r2 ; instruction B

LDR r3, [r4] ; instruction C

SUB r5, r6, #3 ; instruction D At what point will execution pause until the STR access is complete?

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