Free EN0-001 Exam Dumps Preview

In which type of storage will the compiler preferentially place frequently accessed variables?

A software profiling tool records the address held in the Program Counter (PC) every 1 ms. The software function that resides at each recorded address can be determined by the profiling tool. The percentage of

time spent in each function is calculated from the percentage of recorded addresses where each function is resident.

Which one of the following statements is FALSE?

An interrupt handler contains the following instruction sequence at the end. The purpose of these instructions is to clear the interrupt request in the interrupt controller and then safely re-enable interrupts.

STR r0, [r1] ; write to interrupt controller register to clear interrupt request

<x>

CPSIE i ; re-enable IRQ interrupts

Which of the following instructions should be placed at position <x> in order to ensure that the interrupt controller sees the write before interrupts are re-enabled?

Capturing processor execution trace is characterized as being:

Which of the following is preserved in dormant mode?

If the processor is in User mode and then an IRQ interrupt occurs:

A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes.

How many bits are required to index a cache line in a way?

In a Cortex-A processor, assume an initial value of R1 =0x80004000.

If the following instruction causes a data abort, what value will R1 contain on entry to the abort handler?

LDR R0, [R1, #8]!

On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?

When setting the initial location of the stack pointer and the base address of the heap, the ARM EABI requires that the:

A simple system comprises of the following memory map:

Flash - 0x0 to 0x7FFF

RAM - 0x10000 to 0X17FFF

When conforming to the ABI, which of the following is a suitable initial value for the stack pointer?

When using a Generic Interrupt Controller (GIC), how does code cause a software-generated interrupt?

An undefined instruction will cause an Undefined Instruction exception to be taken when:

If the performance of an application remains unchanged when the core clock speed of a Cortex-A9 processor is reduced, what can you deduce about the system?

Which THREE of the following items should be preserved by software when entering dormant mode? (Choose three)

What is the value of R2 after execution of the following instruction sequence?

MOV R3, #0xBA

MOV R2/#0x10

BIC R2, R3, R2

The Memory Protection Unit (MPU) of Cortex-R4 performs which of the following tasks?

Which of the following functions can be performed by a spinlock?

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

A program running on a development board that is connected to a host using a debugger can access a file on the host by using:

When developing a product using the standard ARM C library, what is the minimum effort required to re-target all platform-specific functions in the library?

When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?

To ensure optimum efficiency when programming in C, what is the recommended maximum number of arguments to be passed to a function?

In a system using the Security Extensions, how does the Secure Monitor execute a switch from Secure to Non-secure state?

LDREX and STREX were introduced in which ARM architecture version?

Which TWO of the following mechanisms cause the ARM processor to take an abort? (Choose two)

An Advanced SIMD intrinsic has the prototype:

int16x4_t vmul_n_s16(int16x4_t a, int16_t b);

How many multiplications does this intrinsic compute?

Consider the following instruction sequence:

STR r0, [r2] ; instruction A

DSB

ADD r0, r1, r2 ; instruction B

LDR r3, [r4] ; instruction C

SUB r5, r6, #3 ; instruction D At what point will execution pause until the STR access is complete?

Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?

The following ARM instruction can be used to return from an exception:

movs pc, lr

Apart from the program counter, which register is updated by this instruction?

Which of the following processor resources do NOT have to be saved or modified by the Linux scheduler during context switch?

Using a Generic Interrupt Controller (GIC), when the interrupt handler writes to the End of Interrupt Register (ICCEOIR), which of the following state transitions might occur for that interrupt ID?